A 0.57-mW/Gbps, 2ch × 53-Gbps Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-µm LD-Array-on-Si.
Toshiki KishiMunehiko NagataniShigeru KanazawaKota ShikamaTakuro FujiiHidetaka NishiHiroshi YamazakiNorio SatoHideyuki NosakaShinji MatsuoPublished in: OFC (2020)
Keyphrases
- low power
- power consumption
- image sensor
- high speed
- single chip
- low cost
- low power consumption
- mixed signal
- cmos technology
- power dissipation
- nm technology
- power supply
- signal processor
- digital signal processing
- wireless transmission
- programmable logic
- wide dynamic range
- power reduction
- ultra low power
- focal plane
- high power
- vlsi circuits
- cmos image sensor
- power management
- real time
- solid state
- multi channel
- digital camera
- infrared
- gate array