Hiromi Inaba

Publication Activity (10 Years)

Years Active: 2012-2017
Publications (10 Years): 4

Top Topics

Band Pass Filters

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ISCAS (2017)
Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine
Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. ISOCC (2016)
Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya
36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. ISOCC (2016)
Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, Keiji Kishine
Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system. ISOCC (2016)
Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS (2014)
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura
Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. MWSCAS (2013)
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura
Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. MWSCAS (2012)