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Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.
Kosuke Furuichi
Hiromu Uemura
Natsuyuki Koda
Hiromi Inaba
Keiji Kishine
Published in:
ISOCC (2016)
Keyphrases
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circuit design
power dissipation
cmos technology
high speed
nm technology
chip design
power consumption
low power
real time
detection algorithm
design methodology
low voltage
detection method
single chip
phase locked loop
logic circuits
case study