Mitsuo Nakamura

Publication Activity (10 Years)

Years Active: 2012-2018
Publications (10 Years): 1

Top Topics

Power Reduction

Sensor Networks

Design Procedure

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEICE Trans. Electron.

Publications

Nobutaro Shibata, Mitsuo Nakamura
An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2018)
Mitsuo Nakamura, Mamoru Ugajin, Mitsuru Harada
A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor Networks. IEICE Trans. Electron. (1) (2013)
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura
Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. MWSCAS (2013)
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura
Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. MWSCAS (2012)