Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control.

Keiji Kishine Hiromi Inaba Yusuke Ohtomo Makoto Nakamura Mitsuo Nakamura

Published in: MWSCAS (2012)

Keyphrases

high speed
cost function
detection method
pairwise
significant improvement
design procedure
preprocessing
objective function
computational complexity
high accuracy
real time
genetic algorithm
control system
highly efficient
circuit design
control loop