Nobutaro Shibata

Publication Activity (10 Years)

Years Active: 1996-2018
Publications (10 Years): 4

Top Topics

Memory Subsystem

Cache Invalidation

Magnetic Recording

Top Venues

IEICE Trans. Electron.

IEEE Trans. Very Large Scale Integr. Syst.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Nobutaro Shibata, Mitsuo Nakamura
An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2018)
Nobutaro Shibata, Mayumi Watanabe, Takako Ishihara
Dual-Port SRAM Macro for Serial Access Applications. IEICE Trans. Electron. (11) (2017)
Nobutaro Shibata, Takako Ishihara
A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme. IEICE Trans. Electron. (2) (2016)
Nobutaro Shibata, Yoshinori Gotoh, Takako Ishihara
A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications. IEICE Trans. Electron. (6) (2016)
Nobutaro Shibata, Yoshinori Gotoh
High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Nobutaro Shibata, Yusuke Ohtomo, Mika Nishisaka, Yasuhiro Sato
CMOS/SIMOX Techniques. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama
A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells. IEEE J. Solid State Circuits 45 (9) (2010)
Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki
A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme. IEEE J. Solid State Circuits 41 (3) (2006)
Takakuni Douseki, Toshishige Shimamura, Nobutaro Shibata
A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation. IEICE Trans. Electron. (4) (2005)
Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell. IEEE J. Solid State Circuits 37 (6) (2002)
Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine
A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. IEEE J. Solid State Circuits 36 (10) (2001)
Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada
1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs. IEEE J. Solid State Circuits 35 (10) (2000)
Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe
A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers. IEEE J. Solid State Circuits 34 (6) (1999)
Hiroki Morimura, Nobutaro Shibata
A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's. IEEE J. Solid State Circuits 33 (8) (1998)
Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato
Two-chip MPEG-2 video encoder. IEEE Micro 16 (2) (1996)
Hiroki Morimura, Nobutaro Shibata
A 1-V 1-Mb SRAM for portable equipment. ISLPED (1996)