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High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost.
Nobutaro Shibata
Yoshinori Gotoh
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
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high density
gate array
low density
low cost
high power
close proximity
low power
circuit design
database
thin film
design considerations
design methodology
logic circuits
power consumption
image processing
metadata
chip design
real time