25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.
Tomonori TanakaKosuke FuruichiHiromu UemuraRyosuke NoguchiNatsuyuki KodaKoki ArauchiDaichi OmotoHiromi InabaKeiji KishineShinsuke NakanoMasafumi NogawaHideyuki NosakaPublished in: ISCAS (2017)