MOS D-flip-flop in 65-nm CMOS.

Ryosuke Noguchi Kosuke Furuichi Hiromu Uemura Toshiyuki Inoue Akira Tsuchiya Keiji Kishine Hiroaki Katsurai Shinsuke Nakano Hideyuki Nosaka

Published in: VLSI-DAT (2018)

Keyphrases

flip flops
cmos technology
low power
power dissipation
power consumption
low voltage
parallel processing
silicon on insulator
image sensor
high speed
low cost
neural network
digital signal processing
image sequences
input output
imaging systems
case study
computer vision
metal oxide semiconductor
real time