A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si.
Toshiki KishiMunehiko NagataniShigeru KanazawaShinsuke NakanoHiroaki KatsuraiTakuro FujiiHidetaka NishiTakaaki KakitsukaKoichi HasebeKota ShikamaYuko KawajiriAtsushi AratakeHideyuki NosakaHiroshi FukudaShinji MatsuoPublished in: OFC (2018)
Keyphrases
- low power
- power consumption
- image sensor
- single chip
- high speed
- low cost
- mixed signal
- cmos technology
- low power consumption
- power supply
- power dissipation
- programmable logic
- wide dynamic range
- nm technology
- signal processor
- focal plane
- power management
- vlsi circuits
- ultra low power
- high power
- digital signal processing
- vlsi architecture
- power reduction
- logic circuits
- wireless transmission
- cmos image sensor
- real time
- solid state
- communication systems
- high density
- gate array
- intelligent control