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CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design.
Kazuhiro Ueda
Hitoshi Kitazawa
Ikuo Harada
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1985)
Keyphrases
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layout design
vlsi design
high speed
single chip
vlsi implementation
chip design
integer programming
low cost
signal processing
tunnel boring machine
cell formation
hierarchical structure
route planning
plan recognition
power dissipation
objective function
shortest path
expert systems