Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip.
Tomoyuki NakabayashiTakahiro SasakiHitoshi NakamuraKazuhiko OhnoToshio KondoPublished in: Int. J. Netw. Comput. (2013)
Keyphrases
- fine grain
- coarse grain
- distributed memory
- high speed
- multithreading
- single chip
- parallel computation
- parallel architecture
- energy consumption
- low cost
- parallel processing
- processor core
- multistage
- reconfigurable hardware
- mobile devices
- nested transactions
- parallel algorithm
- real time
- computational power
- parallel implementation
- low power