Tomoyuki Nakabayashi

Publication Activity (10 Years)

Years Active: 2010-2014
Publications (10 Years): 0

Top Topics

Distributed Memory

Pipeline Architecture

Top Venues

IET Comput. Digit. Tech.

Publications

Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. ASP-DAC (2014)
Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
Detail Design and Evaluation of Fab Cache. CANDAR (2014)
Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
Dynamic BTB Resizing for Variable Stages Superscalar Architecture. CANDAR (2013)
Tomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo
Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip. Int. J. Netw. Comput. 3 (2) (2013)
Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. IET Comput. Digit. Tech. 7 (1) (2013)
Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
FabCache: Cache Design Automation for Heterogeneous Multi-core Processors. CANDAR (2013)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture. ICNC (2012)
Tomoyuki Nakabayashi, Takahiro Sasaki, I. K. Ohno, Toshio Kondo
Design and evaluation of variable stages pipeline processor with low-energy techniques. IET Comput. Digit. Tech. 6 (1) (2012)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Design and evaluation of variable stages pipeline processor chip. ASP-DAC (2011)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Low power semi-static TSPC D-FFs using split-output latch. ISOCC (2011)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Design and Evaluation of Variable Stages Pipeline Processor Chip. ISIA (2010)