Design and Evaluation of Variable Stages Pipeline Processor Chip.

Tomoyuki Nakabayashi Takahiro Sasaki Kazuhiko Ohno Toshio Kondo

Published in: ISIA (2010)

Keyphrases

single chip
functional verification
high speed
case study
low power
evolvable hardware
chip design
low cost
design process
parallel processing
computer systems
computer architecture
physical design