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Koyo Nitta
Publication Activity (10 Years)
Years Active: 1999-2023
Publications (10 Years): 16
Top Topics
Parallel Processing
Motion Estimation
Compression Efficiency
Low Delay
Top Venues
IEICE Trans. Commun.
COOL CHIPS
IEICE Trans. Electron.
ASAP
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Publications
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Hiroyuki Uzawa
,
Shuhei Yoshida
,
Yukou Iinuma
,
Saki Hatta
,
Daisuke Kobayashi
,
Yuya Omori
,
Yusuke Horishita
,
Ken Nakamura
,
Shuichi Takada
,
Hassan Toorabally
,
Koyo Nitta
,
Koji Yamazaki
,
Kimikazu Sano
High-definition technology of AI inference scheme for object detection on edge/terminal.
IEICE Electron. Express
20 (13) (2023)
Ken Nakamura
,
Yuya Omori
,
Daisuke Kobayashi
,
Koyo Nitta
,
Kimikazu Sano
,
Masayuki Sato
,
Hiroe Iwasaki
,
Hiroaki Kobayashi
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture.
IEICE Trans. Electron.
106 (6) (2023)
Ken Nakamura
,
Yuya Omori
,
Daisuke Kobayashi
,
Koyo Nitta
,
Kimikazu Sano
,
Masayuki Sato
,
Hiroe Iwasaki
,
Hiroaki Kobayashi
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.
COOL CHIPS
(2022)
Hasitha Muthumala Waidyasooriya
,
Masanori Hariyama
,
Hiroe Iwasaki
,
Daisuke Kobayashi
,
Yuya Omori
,
Ken Nakamura
,
Koyo Nitta
,
Kimikazu Sano
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization.
MWSCAS
(2022)
Saki Hatta
,
Nobuyuki Tanaka
,
Hiroyuki Uzawa
,
Koyo Nitta
Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems.
IEICE Trans. Commun.
(3) (2021)
Shuhei Yoshida
,
Yuta Ukon
,
Shoko Ohteru
,
Hiroyuki Uzawa
,
Namiko Ikeda
,
Koyo Nitta
FPGA-based network microburst analysis system with efficient packet capturing.
JOCN
13 (10) (2021)
Hiroyuki Uzawa
,
Kazuhiko Terada
,
Koyo Nitta
A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation.
IEICE Trans. Commun.
(5) (2021)
Yuta Ukon
,
Koji Yamazaki
,
Koyo Nitta
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture.
IEICE Trans. Commun.
(1) (2020)
Shuhei Yoshida
,
Yuta Ukon
,
Shoko Ohteru
,
Hiroyuki Uzawa
,
Namiko Ikeda
,
Koyo Nitta
FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing.
ASAP
(2020)
Ken Nakamura
,
Daisuke Kobayashi
,
Yuya Omori
,
Tatsuya Osawa
,
Takayuki Onishi
,
Koyo Nitta
,
Hiroe Iwasaki
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.
IEICE Trans. Electron.
(3) (2020)
Ken Nakamura
,
Yuya Omori
,
Daisuke Kobayashi
,
Tatsuya Osawa
,
Takayuki Onishi
,
Koyo Nitta
,
Hiroe Iwasaki
,
Atsushi Shimizu
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.
COOL CHIPS
(2019)
Koji Yamazaki
,
Yuta Ukon
,
Shuhei Yoshida
,
Saki Hatta
,
Yusuke Sekihara
,
Shoko Ohteru
,
Tomoaki Kawamura
,
Takahiro Hatano
,
Koyo Nitta
,
Akihiko Miyazaki
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane.
HPSR
(2018)
Yuta Ukon
,
Koji Yamazaki
,
Koyo Nitta
Video Service Function Chaining with a Real-time Packet Reordering Circuit.
ISCAS
(2018)
Takayuki Onishi
,
Takashi Sano
,
Yukikuni Nishida
,
Kazuya Yokohari
,
Ken Nakamura
,
Koyo Nitta
,
Kimiko Kawashima
,
Jun Okamoto
,
Naoki Ono
,
Atsushi Sagata
,
Hiroe Iwasaki
,
Mitsuo Ikeda
,
Atsushi Shimizu
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K.
IEEE Trans. Very Large Scale Integr. Syst.
26 (10) (2018)
Hiroe Iwasaki
,
Takayuki Onishi
,
Ken Nakamura
,
Koyo Nitta
,
Takashi Sano
,
Yukikuni Nishida
,
Kazuya Yokohari
,
Jia Su
,
Naoki Ono
,
Ritsu Kusaba
,
Atsushi Sagata
,
Mitsuo Ikeda
,
Atsushi Shimizu
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure.
Hot Chips Symposium
(2015)
Takayuki Onishi
,
Takashi Sano
,
Yukikuni Nishida
,
Kazuya Yokohari
,
Jia Su
,
Ken Nakamura
,
Koyo Nitta
,
Kimiko Kawashima
,
Jun Okamoto
,
Naoki Ono
,
Ritsu Kusaba
,
Atsushi Sagata
,
Hiroe Iwasaki
,
Mitsuo Ikeda
,
Atsushi Shimizu
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability.
VLSIC
(2015)
Jia Su
,
Koyo Nitta
,
Mitsuo Ikeda
,
Atsushi Shimizu
Residue role assignment based transform partition predetermination on HEVC.
ICIP
(2013)
Mitsuo Ikeda
,
Takayuki Onishi
,
Takashi Sano
,
Atsushi Sagata
,
Hiroe Iwasaki
,
Yasuyuki Nakajima
,
Koyo Nitta
,
Yasuko Takahashi
,
Kazuya Yokohari
,
Daisuke Kobayashi
,
Kazuto Kamikura
,
Hirohisa Jozawa
MVC real-time video encoder for full-HDTV 3D video.
ICCE
(2012)
Koyo Nitta
,
Hiroe Iwasaki
,
Takayuki Onishi
,
Takashi Sano
,
Atsushi Sagata
,
Yasuyuki Nakajima
,
Minoru Inamori
,
Ryuichi Tanida
,
Atsushi Shimizu
,
Ken Nakamura
,
Mitsuo Ikeda
,
Jiro Naganuma
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures.
IEICE Trans. Electron.
(4) (2012)
Takayuki Onishi
,
Takashi Sano
,
Koyo Nitta
,
Mitsuo Ikeda
,
Jiro Naganuma
Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI.
ISCAS
(2008)
Hiroe Iwasaki
,
Jiro Naganuma
,
Koyo Nitta
,
Ken Nakamura
,
Takeshi Yoshitome
,
Mitsuo Ogura
,
Yasuyuki Nakajima
,
Yutaka Tashiro
,
Takayuki Onishi
,
Mitsuo Ikeda
,
Toshihiro Minami
,
Makoto Endo
,
Yoshiyuki Yashima
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.
IEEE Trans. Very Large Scale Integr. Syst.
15 (9) (2007)
Hiroe Iwasaki
,
Jiro Naganuma
,
Koyo Nitta
,
Ken Nakamura
,
Takeshi Yoshitome
,
Mitsuo Ogura
,
Yasuyuki Nakajima
,
Yutaka Tashiro
,
Takayuki Onishi
,
Mitsuo Ikeda
,
Makoto Endo
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.
DATE
(2003)
Mitsuo Ikeda
,
Toshio Kondo
,
Koyo Nitta
,
Kazuhito Suguri
,
Takeshi Yoshitome
,
Toshihiro Minami
,
Hiroe Iwasaki
,
Katsuyuki Ochiai
,
Jiro Naganuma
,
Makoto Endo
,
Yutaka Tashiro
,
Hiroshi Watanabe
,
Naoki Kobayashi
,
Tsuneo Okubo
,
Ryota Kasai
SuperENC: MPEG-2 video encoder chip.
IEEE Micro
19 (4) (1999)
Takeshi Yoshitome
,
Toshihiro Minami
,
Mitsuo Ikeda
,
Koyo Nitta
,
Kazuhito Suguri
A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI.
IEEE Trans. Consumer Electron.
45 (4) (1999)
Mitsuo Ikeda
,
Toshio Kondo
,
Koyo Nitta
,
Kazuhito Suguri
,
Takeshi Yoshitome
,
Toshihiro Minami
,
Jiro Naganuma
,
Takeshi Ogura
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.
DATE
(1999)