Masayuki Sato

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 45

Top Topics

Top Venues

Supercomput. Front. Innov.

Publications

Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Ising-Based Kernel Clustering. Algorithms 16 (4) (2023)
Bin Qi, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
A dynamic parameter tuning method for SpMM parallel execution. Concurr. Comput. Pract. Exp. 35 (17) (2023)
Yusuke Fukasawa, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Appropriate Graph-Algorithm Selection for Edge Devices Using Machine Learning. MCSoC (2023)
Makoto Onoda, Kazuhiko Komatsu, Masahito Kumagai, Masayuki Sato, Hiroaki Kobayashi
A Constraint Partition Method for Combinatorial Optimization Problems. MCSoC (2023)
Yihui Liu, Kazuhiko Komatsu, Masahito Kumagai, Masayuki Sato, Hiroaki Kobayashi
Performance Evaluation of Tsunami Evacuation Route Planning on Multiple Annealing Machines. CF (2023)
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106 (6) (2023)
Chunting Duan, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Multi-scale Loss based Electron Microscopic Image Pair Matching Method. ICMLA (2023)
Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT (2022)
Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. IEICE Trans. Electron. (6) (2022)
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS (2022)
Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi
Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation. IA3@SC (2022)
Osamu Watanabe, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Optimizing Load Balance in a Parallel CFD Code for a Large-scale Turbine Simulation on a Vector Supercomputer. Supercomput. Front. Innov. 8 (2) (2021)
Kazuhiko Komatsu, Masahito Kumagai, Ji Qi, Masayuki Sato, Hiroaki Kobayashi
An Externally-Constrained Ising Clustering Method for Material Informatics. CANDAR (Workshops) (2021)
Masahito Kumagai, Kazuhiko Komatsu, Fumiyo Takano, Takuya Araki, Masayuki Sato, Hiroaki Kobayashi
An External Definition of the One-Hot Constraint and Fast QUBO Generation for High-Performance Combinatorial Clustering. Int. J. Netw. Comput. 11 (2) (2021)
Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi
Register Flush-free Runahead Execution for Modern Vector Processors. SBAC-PAD (2021)
Kou Murakami, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
A Processor Selection Method based on Execution Time Estimation for Machine Learning Programs. IPDPS Workshops (2021)
Hao Tang, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Efficient Mixed-Precision Tall-and-Skinny Matrix-Matrix Multiplication for GPUs. Int. J. Netw. Comput. 11 (2) (2021)
Zhilin He, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Optimizations of a Linear Matrix Solver in a Composite Simulation for a Vector Computer. PAAP (2021)
Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
Ising-Based Combinatorial Clustering Using the Kernel Method. MCSoC (2021)
Kazuhiko Komatsu, Akito Onodera, Erich Focht, Soya Fujimoto, Yoko Isobe, Shintaro Momose, Masayuki Sato, Hiroaki Kobayashi
Performance and Power Analysis of a Vector Computing System. Supercomput. Front. Innov. 8 (2) (2021)
Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. COOL CHIPS (2021)
Masayuki Sato, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi
Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. COOL CHIPS (2020)
Masahito Kumagai, Kazuhiko Komatsu, Fumiyo Takano, Takuya Araki, Masayuki Sato, Hiroaki Kobayashi
Combinatorial Clustering Based on an Externally-Defined One-Hot Constraint. CANDAR (2020)
Yiran Cheng, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
A Deep Reinforcement Learning Based Feature Selector. PAAP (2020)
Akito Onodera, Kazuhiko Komatsu, Souya Fujimoto, Yoko Isobe, Masayuki Sato, Hiroaki Kobayashi
Optimization of the Himeno Benchmark for SX-Aurora TSUBASA. Bench (2020)
Bin Qi, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
A Dynamic Parameter Tuning Method for High Performance SpMM. PDCAT (2020)
Hao Tang, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi
An Efficient Skinny Matrix-Matrix Multiplication Method by Folding Input Matrices into Tensor Core Operations. CANDAR (Workshops) (2020)
Takumi Kishitani, Kazuhiko Komatsu, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi
Importance of Selecting Data Layouts in the Tsunami Simulation Code. IPDPS Workshops (2020)
Masayuki Sato, Takuya Toyoshima, Hikaru Takayashiki, Ryusuke Egawa, Hiroaki Kobayashi
An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems. Supercomput. Front. Innov. 6 (4) (2019)
Masayuki Sato, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi
Perceptron-based Cache Bypassing for Way-Adaptable Caches. COOL CHIPS (2019)
Osamu Watanabe, Yuta Hougi, Kazuhiko Komatsu, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi
Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA. MCHPC@SC (2019)
Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi
A Hardware Prefetching Mechanism for Vector Gather Instructions. IA3@SC (2019)
Akihiro Musa, Takashi Abe, Takumi Kishitani, Takuya Inoue, Masayuki Sato, Kazuhiko Komatsu, Yoichi Murashima, Shunichi Koshimura, Hiroaki Kobayashi
Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA. ICCS (2) (2019)
Ryusuke Egawa, Ryoma Saito, Masayuki Sato, Hiroaki Kobayashi
A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism. HEART (2019)
Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Hiroaki Kobayashi
An Appropriate Computing System and Its System Parameters Selection Based on Bottleneck Prediction of Applications. IPDPS Workshops (2019)
Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi
A Skewed Multi-banked Cache for Many-core Vector Processors. Supercomput. Front. Innov. 6 (3) (2019)
Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi
An energy-aware set-level refreshing mechanism for eDRAM last-level caches. COOL CHIPS (2018)
Kazuhiko Komatsu, Shintaro Momose, Yoko Isobe, Osamu Watanabe, Akihiro Musa, Mitsuo Yokokawa, Toshikazu Aoyama, Masayuki Sato, Hiroaki Kobayashi
Performance evaluation of a vector supercomputer SX-aurora TSUBASA. SC (2018)
Masayuki Sato, Yoshiki Shoji, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi
Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor. MCSoC (2018)
Jubee Tada, Masayuki Sato, Ryusuke Egawa
An Adaptive Demotion Policy for High-Associativity Caches. HEART (2017)
Masayuki Sato, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi
An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. COOL Chips (2017)
Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi
An application-adaptive data allocation method for multi-channel memory. COOL Chips (2017)
Ryusuke Egawa, Wataru Uno, Masayuki Sato, Hiroaki Kobayashi, Jubee Tada
A power-aware LLC control mechanism for the 3D-stacked memory system. 3DIC (2016)
Masayuki Sato, Shin Nishimura, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
A cache partitioning mechanism to protect shared data for CMPs. COOL Chips (2016)
Masayuki Sato, Chengguang Han, Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
An energy-efficient dynamic memory address mapping mechanism. COOL Chips (2015)
Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms. IEICE Trans. Electron. (7) (2015)
Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
An energy optimization method for vector processing mechanisms. COOL Chips (2014)
Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications. IEICE Trans. Inf. Syst. (11) (2014)
Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
On-chip checkpointing with 3D-stacked memories. 3DIC (2014)
Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts. IEICE Trans. Inf. Syst. (9) (2013)
Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
A flexible insertion policy for dynamic cache resizing mechanisms. COOL Chips (2013)
Ryusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi
Vertically integrated processor and memory module design for vector supercomputers. 3DIC (2013)
Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
A capacity-efficient insertion policy for dynamic cache resizing mechanisms. Conf. Computing Frontiers (2012)
Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
A Majority-Based Control Scheme for Way-Adaptable Caches. Facing the Multicore-Challenge (2010)
Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
A voting-based working set assessment scheme for dynamic cache resizing mechanisms. ICCD (2010)