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A Skewed Multi-banked Cache for Many-core Vector Processors.
Hikaru Takayashiki
Masayuki Sato
Kazuhiko Komatsu
Hiroaki Kobayashi
Published in:
Supercomput. Front. Innov. (2019)
Keyphrases
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embedded processors
memory subsystem
parallel algorithm
query processing
memory hierarchy
multithreading
memory access
hit rate
feature vectors
prefetching
class distribution
parallel computing
high end
parallel processors
parallel processing
main memory
multiprocessor systems
cache misses
input output