Hasitha Muthumala Waidyasooriya

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 26

Top Topics

Database Management

Pipelined Architecture

Design Space Exploration

Spatial And Temporal

Top Venues

J. Supercomput.

Publications

Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs. J. Supercomput. 80 (12) (2024)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU. J. Supercomput. 78 (6) (2022)
Kosiro Obata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++. MWSCAS (2022)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS (2022)
Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama
Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. PDCAT (2022)
Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. J. Supercomput. 78 (1) (2022)
Mitsuhiro Okada, Takayuki Suzuki, Naoya Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services. IEEE Trans. Cloud Comput. 10 (2) (2022)
Hasitha Muthumala Waidyasooriya, Yuta Ohma, Masanori Hariyama
FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model. MCSoC (2022)
Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory. IEEE Access 10 (2022)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism. IEEE Access 8 (2020)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki
OpenCL-based design of an FPGA accelerator for quantum annealing simulation. J. Supercomput. 75 (8) (2019)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability. IEEE Access 7 (2019)
Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama
Benchmarks for FPGA-Targeted High-Level-Synthesis. CANDAR (2019)
Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA. CANDAR Workshops (2019)
Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. CANDAR (2019)
Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
FPGA-Based Acceleration of Word2vec using OpenCL. ISCAS (2019)
Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada
Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems. SCFA (2018)
Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama
Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. ISPACS (2018)
Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. Int. J. Reconfigurable Comput. 2017 (2017)
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama
OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. IEEE Trans. Parallel Distributed Syst. 28 (5) (2017)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL. Int. J. Networked Distributed Comput. 5 (1) (2017)
Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki
Architecture of an FPGA accelerator for LDA-based inference. SNPD (2017)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform. IEEE Trans. Parallel Distributed Syst. 27 (5) (2016)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL. ICIS (2016)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL. ICIS (2016)
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama
Hardware-oriented succinct-data-structure based on block-size-constrained compression. SoCPaR (2015)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. 2014 (2014)
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS (2014)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC (2013)
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS (2012)
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. (2) (2012)
Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. (12) (2012)
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. 21 (10) (2011)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2011)
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA (2010)
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA (2010)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. (4) (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA (2008)
Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. (4) (2008)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)