Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability.
Hasitha Muthumala WaidyasooriyaMasanori HariyamaPublished in: IEEE Access (2019)
Keyphrases
- pipelined architecture
- field programmable gate array
- hardware implementation
- computation intensive
- hardware architecture
- hardware design
- fpga implementation
- fpga technology
- spatio temporal
- hardware architectures
- software implementation
- real time
- xilinx virtex
- parallel architecture
- dedicated hardware
- fpga device
- parallel computing
- neural network
- management system
- temporal data
- software architecture
- temporal information
- spatial and temporal
- temporal patterns
- embedded systems
- fault tolerance
- parallel implementation
- scalable distributed
- reconfigurable hardware
- temporal constraints
- high speed
- low cost
- network architecture
- temporal relations