A cache memory with unit tile and line accessibility.
BaoKang WangYuki FukazawaToshio KondoTakahiro SasakiPublished in: ICIS (2016)
Keyphrases
- memory hierarchy
- main memory
- memory subsystem
- memory access
- cache conscious
- computing power
- virtual memory
- processing units
- memory usage
- garbage collection
- line segments
- data access
- limited memory
- memory management
- resource consumption
- memory space
- external memory
- hash table
- cache misses
- back end
- secondary storage
- prefetching
- memory requirements
- read write
- data structure
- processor core
- high speed
- operating system
- government services
- multithreading
- computational power
- processing elements
- database