Design of controller for L2 cache mapped in Tezzaron stacked DRAM.

Nyunyi M. Tshibangu Paul D. Franzon Eric Rotenberg William Rhett Davis

Published in: 3DIC (2013)

Keyphrases

real time
memory subsystem
closed loop
control system
query processing
data structure
data model
mathematical model
main memory
data access
case study
design principles
control method
adaptive control
design considerations
memory hierarchy
database