Sumedh W. Sathaye

Publication Activity (10 Years)

Years Active: 1995-2006
Publications (10 Years): 0

Publications

Erik R. Altman, Sumedh W. Sathaye
Preface. IBM J. Res. Dev. 50 (2-3) (2006)
Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye
Dynamic Binary Translation and Optimization. IEEE Trans. Computers 50 (6) (2001)
Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. Very Large Scale Integr. Syst. 8 (2) (2000)
Michael Gschwind, Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye
Binary translation and architecture convergence issues for IBM system/390. ICS (2000)
Thomas M. Conte, Sumedh W. Sathaye
Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. IEEE Trans. Computers 49 (8) (2000)
Michael Gschwind, Erik R. Altman, Sumedh W. Sathaye, Paul Ledak, David Appenzeller
Dynamic and Transparent Binary Translation. Computer 33 (3) (2000)
Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind
Execution-Based Scheduling for VLIW Architectures. Euro-Par (1999)
Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind
Optimizations and Oracle Parallelism with Dynamic Translation. MICRO (1999)
Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers 47 (12) (1998)
Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT (1998)
Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte
Path Prediction for High Issue-Rate Processors. IEEE PACT (1997)
Thomas M. Conte, Sumedh W. Sathaye
Optimization of VLIW compatibility systems employing dynamic rescheduling. Int. J. Parallel Program. 25 (2) (1997)
Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO (1996)
Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. MICRO (1996)
Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye
A technique to determine power-efficient, high-performance superscalar processors. HICSS (1) (1995)
Thomas M. Conte, Sumedh W. Sathaye
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. MICRO (1995)