Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Mustafa BadarogluKris TiriStéphane DonnayPiet WambacqHugo De ManIngrid VerbauwhedeGeorges G. E. GielenPublished in: DAC (2002)
Keyphrases
- noise reduction
- digital circuits
- signal to noise ratio
- circuit design
- edge preserving
- power consumption
- high speed
- edge detection
- noise level
- wiener filter
- noise removal
- median filter
- noisy environments
- finite state machines
- low power
- multiscale
- model based diagnosis
- data flow
- speech enhancement
- impulse noise
- impulsive noise
- edge enhancement
- low voltage