Stéphane Donnay

Publication Activity (10 Years)

Years Active: 1994-2007
Publications (10 Years): 0

Publications

Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance CoRR (2007)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS (2007)
Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits 41 (9) (2006)
Geert Van der Plas, Stefaan Decoutere, Stéphane Donnay
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process. ISSCC (2006)
Kris Baert, Bert Gyselinckx, Tom Torfs, Vladimir Leonov, Refet Firat Yazicioglu, Steven Brebels, Stéphane Donnay, J. Vanfletern, M. Pastreen, Eric Beyne, Chris Van Hoof
Technologies for highly miniaturized autonomous sensor networks. Microelectron. J. 37 (12) (2006)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2006)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2005)
Andrew Fort, Claude Desset, Julien Ryckaert, Philippe De Doncker, Leo Van Biesen, Stéphane Donnay
Ultra wide-band body area channel model. ICC (2005)
Jan Tubbax, Boris Come, Liesbet Van der Perre, Stéphane Donnay, Marc Engels, Hugo De Man, Marc Moonen
Compensation of IQ imbalance and phase noise in OFDM systems. IEEE Trans. Wirel. Commun. 4 (3) (2005)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (1) (2005)
Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Maarten Kuijk
Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. IEEE J. Solid State Circuits 40 (7) (2005)
Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
Substrate noise immune design of an LC-tank VCO using sensitivity functions. CICC (2005)
Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE (2005)
Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere
A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. IEEE J. Solid State Circuits 40 (7) (2005)
Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Piet Wambacq, Morin Dehan, Lars Aspemyr, Andries J. Scholten, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt
Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors. IEEE J. Solid State Circuits 40 (9) (2005)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC (2004)
Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Lars Aspemyr, Andries J. Scholten, Piet Wambacq, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt
A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor. CICC (2004)
Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
Performance degradation of an LC-tank VCO by impact of digital switching noise. ESSCIRC (2004)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE (2004)
Jan Craninckx, Vincent Gravot, Stéphane Donnay
A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications]. ESSCIRC (2004)
Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS. ESSCIRC (2004)
Gerd Vandersteen, Rik Pintelon, Dimitri Linten, Stéphane Donnay
Extended Subspace Identification of Improper Linear Systems. DATE (2004)
Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC (2004)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39 (7) (2004)
Jan Tubbax, Liesbet Van der Perre, Stéphane Donnay, Marc Engels, Marc Moonen, Hugo De Man
Joint compensation of IQ imbalance, frequency offset and phase noise in OFDM receivers. Eur. Trans. Telecommun. 15 (3) (2004)
Jan Tubbax, Boris Come, Liesbet Van der Perre, Stéphane Donnay, Marc Moonen, Hugo De Man
Compensation of transmitter IQ imbalance for OFDM systems. ICASSP (2) (2004)
Jan Tubbax, Liesbet Van der Perre, Stéphane Donnay, Marc Engels
Single-carrier communication using decision-feedback equalization for multiple antennas. ICC (2003)
Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC (2003)
Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fonden, Svante Signell
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits 38 (7) (2003)
Jan Craninckx, Stéphane Donnay
4G terminals: how are we going to design them? DAC (2003)
Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. DATE (2003)
Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (9) (2003)
Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. DATE (2003)
Jan Tubbax, Andrew Fort, Liesbet Van der Perre, Stéphane Donnay, Marc Engels, Marc Moonen, Hugo De Man
Joint compensation of IQ imbalance and frequency offset in OFDM systems. GLOBECOM (2003)
Manuel Innocent, Piet Wambacq, Stéphane Donnay, Willy Sansen, Hugo De Man
A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology. ESSCIRC (2003)
Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man
An analytic Volterra-series-based model for a MEMS variable capacitor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (2) (2003)
Jan Tubbax, Boris Come, Liesbet Van der Perre, Luc Deneire, Stéphane Donnay, Marc Engels
Compensation of IQ imbalance in OFDM systems. ICC (2003)
Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits 37 (11) (2002)
Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . DATE (2002)
Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC (2002)
Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. DATE (2002)
Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits 37 (8) (2002)
Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens
Efficient bit-error-rate estimation of multicarrier transceivers. DATE (2001)
Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt
A Mixed-Signal Design Roadmap. IEEE Des. Test Comput. 18 (6) (2001)
Jan Tubbax, Boris Come, Liesbet Van der Perre, Luc Deneire, Stéphane Donnay, Marc Engels
OFDM versus Single Carrier with Cyclic Prefix: a system-based comparison. VTC Fall (2001)
Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE (2001)
Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. DAC (2000)
Marc van Heijningen, John Compiet, Piet Wambacq, Stéphane Donnay, Marc Engels, Ivo Bolsens
Analysis and experimental verification of digital substrate noise generation for epi-type substrates. IEEE J. Solid State Circuits 35 (7) (2000)
Stéphane Donnay, Philip Pieters, Kristof Vaesen, Wim Diels, Piet Wambacq, Walter De Raedt, Eric Beyne, Marc Engels, Ivo Bolsens
Chip-package codesign of a low-power 5-GHz RF front end. Proc. IEEE 88 (10) (2000)
Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. DATE (2000)
Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens
High-level simulation of substrate noise generation including power supply noise coupling. DAC (2000)
Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Y. Zinzius, Georges G. E. Gielen, Willy Sansen, T. Fondén, Svante Signell
BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS (1999)
Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens
A Single-Package Solution for Wireless Transceivers. DATE (1999)
Piet Wambacq, Gerd Vandersteen, Stéphane Donnay, Marc Engels, Ivo Bolsens, Erik Lauwers, Piet Vanassche, Georges G. E. Gielen
High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications. ICECS (1999)
Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen
High-Level Power Minimization of Analog Sensor Interface Architectures. Integr. Comput. Aided Eng. 5 (4) (1998)
Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. DATE (1998)
Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven
High-level synthesis of analog sensor interface front-ends. ED&TC (1997)
Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen
A high-level design and optimization tool for analog RF receiver front-ends. ICCAD (1995)
Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts
A Methodology for Analog Design Automation in Mixed-Signal ASICs. EDAC-ETC-EUROASIC (1994)