Kris Tiri

Publication Activity (10 Years)

Years Active: 2002-2007
Publications (10 Years): 0

Publications

Patrick Schaumont, Kris Tiri
Masking and Dual-Rail Logic Don't Add Up. CHES (2007)
Kris Tiri
Side-Channel Attack Pitfalls. DAC (2007)
Michael Neve, Kris Tiri
On the complexity of side-channel attacks on AES-256 - methodology and quantitative results on cache attacks. IACR Cryptol. ePrint Arch. 2007 (2007)
Kris Tiri, Onur Aciiçmez, Michael Neve, Flemming Andersen
An Analytical Model for Time-Driven Cache Attacks. FSE (2007)
Kris Tiri, Ingrid Verbauwhede
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs CoRR (2007)
Kris Tiri, Ingrid Verbauwhede
Design Method for Constant Power Consumption of Differential Logic Circuits CoRR (2007)
Kris Tiri, Patrick Schaumont
Changing the Odds Against Masked Logic. Selected Areas in Cryptography (2006)
Kris Tiri, Ingrid Verbauwhede
A digital design flow for secure integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (7) (2006)
David Hwang, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
Securing Embedded Systems. IEEE Secur. Priv. 4 (2) (2006)
Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede
Side-Channel Leakage Tolerant Architectures. ITNG (2006)
David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. IEEE J. Solid State Circuits 41 (4) (2006)
Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Kris Tiri, Ingrid Verbauwhede
Simulation models for side-channel information leaks. DAC (2005)
Kris Tiri, Ingrid Verbauwhede
Design Method for Constant Power Consumption of Differential Logic Circuits. DATE (2005)
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. CHES (2005)
Kris Tiri, Ingrid Verbauwhede
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. DATE (2005)
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. DAC (2005)
Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. ACM Great Lakes Symposium on VLSI (2005)
Kris Tiri, Ingrid Verbauwhede
Synthesis of Secure FPGA Implementations. IACR Cryptol. ePrint Arch. 2004 (2004)
Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. CASES (2004)
Kris Tiri, Ingrid Verbauwhede
Secure Logic Synthesis. FPL (2004)
Kris Tiri, Ingrid Verbauwhede
A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC's. IACR Cryptol. ePrint Arch. 2004 (2004)
Kris Tiri, Ingrid Verbauwhede
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. DATE (2004)
Kris Tiri, Ingrid Verbauwhede
Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]. ESSCIRC (2004)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39 (7) (2004)
Kris Tiri, Ingrid Verbauwhede
Place and Route for Secure Standard Cell Design. CARDIS (2004)
Kris Tiri, Ingrid Verbauwhede
Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC's against Differential Power Analysis. IACR Cryptol. ePrint Arch. 2004 (2004)
Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC (2003)
Kris Tiri, Ingrid Verbauwhede
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. CHES (2003)
Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC (2002)