Alireza Hodjat

Publication Activity (10 Years)

Years Active: 2003-2007
Publications (10 Years): 0

Publications

Alireza Hodjat, Lejla Batina, David Hwang, Ingrid Verbauwhede
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor. Integr. 40 (1) (2007)
Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede
Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers. FPL (2006)
Alireza Hodjat, Ingrid Verbauwhede
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. IEEE Trans. Computers 55 (4) (2006)
David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. IEEE J. Solid State Circuits 41 (4) (2006)
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. CHES (2005)
Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede
Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP. CHES (2005)
Alireza Hodjat, David Hwang, Ingrid Verbauwhede
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks. ITCC (1) (2005)
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. DAC (2005)
Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. ACM Great Lakes Symposium on VLSI (2005)
Patrick Schaumont, Kazuo Sakiyama, Alireza Hodjat, Ingrid Verbauwhede
Embedded Software Integration for Coarse-Grain Reconfigurable Systems. IPDPS (2004)
Alireza Hodjat, Ingrid Verbauwhede
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. FCCM (2004)
Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede
Architectural Design Features of a Programmable High Throughput AES Coprocessor. ITCC (2) (2004)
Alireza Hodjat, Ingrid Verbauwhede
High-Throughput Programmable Cryptocoprocessor. IEEE Micro 24 (3) (2004)
Alireza Hodjat, Ingrid Verbauwhede
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. ISVLSI (2004)
Herwin Chan, Alireza Hodjat, Jun Shi, Richard D. Wesel, Ingrid Verbauwhede
Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network. ITCC (2) (2004)
Patrick Schaumont, Kazuo Sakiyama, Yi Fan, David D. Hwang, Shenglin Yang, Alireza Hodjat, Bo-Cheng Lai, Ingrid Verbauwhede
Testing ThumbPod: Softcore bugs are hard to find. HLDVT (2003)
David D. Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. DAC (2003)