Tsung-Te Liu

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 29

Top Topics

Elliptic Curve Cryptography

Error Detection

Automatic Speech Recognition

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Yu-Hsiang Tseng, Shao-Hong Yang, Tsung-Te Liu
Highly Reliable PUF Circuits Using Efficient Post-Processing Stabilization Technique. ISCAS (2024)
Bing-Chen Wu, Wei-Ting Chen, Tsung-Te Liu
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS. IEEE J. Solid State Circuits 58 (11) (2023)
Shao-Hong Yang, Tsung-Te Liu
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Hua-Chien Chang, Ting Wang, Chi-An Liao, Tsung-Te Liu
A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Rui-Xuan Zheng, Ya-Cheng Ko, Tsung-Te Liu
A Speculative Computation Approach for Energy-Efficient Deep Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (3) (2023)
Chun-Yen Yao, Tsung-Yen Wu, Han-Chung Liang, Yu-Kai Chen, Tsung-Te Liu
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing. IEEE J. Solid State Circuits 58 (5) (2023)
Chi-Chang Lee, Hong-Wei Chen, Chu-Song Chen, Hsin-Min Wang, Tsung-Te Liu, Yu Tsao
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models. CoRR (2023)
Chi-Chang Lee, Hong-Wei Chen, Chu-Song Chen, Hsin-Min Wang, Tsung-Te Liu, Yu Tsao
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models. ASRU (2023)
Ming-Guang Lin, Chi-Tse Huang, Yu-Chuan Chuang, Yi-Ta Chen, Ying-Tuan Hsu, Yu-Kai Chen, Jyun-Jhe Chou, Tsung-Te Liu, Chi-Sheng Shih, An-Yeu Wu
D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Yi-Long Liou, Jui-Yang Hsu, Chen-Sheng Chen, Alexander H. Liu, Hung-Yi Lee, Tsung-Te Liu
A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor. IEEE Trans. Circuits Syst. II Express Briefs 69 (10) (2022)
Shih-Hao Cheng, Meng-Hsueh Lee, Bing-Chen Wu, Tsung-Te Liu
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer. IEEE Trans. Circuits Syst. II Express Briefs 69 (10) (2022)
You-Cheng Lai, Chun-Yen Yao, Shao-Hong Yang, Ying-Wei Wu, Tsung-Te Liu
A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Jyun-Jhe Chou, Ting-Wei Chang, Xin-You Liu, Tsung-Yen Wu, Yu-Kai Chen, Ying-Tuan Hsu, Chih-Wei Chen, Tsung-Te Liu, Chi-Sheng Shih
CIM-Based Smart Pose Detection Sensors. Sensors 22 (9) (2022)
Jung-Chun Liu, Tsung-Te Liu
Multi-Robot Formation Control using Collective Behavior Model and Reinforcement Learning. ISCAS (2022)
Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. J. Electron. Test. 37 (4) (2021)
Bing-Chen Wu, Tsung-Te Liu
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency. VLSI Circuits (2021)
Chia-Heng Lee, Ying-Tuan Hsu, Tsung-Te Liu, Tzi-Dar Chiueh
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications. APCCAS (2020)
Zhen-Yu Liang, Hao-Hsuan Wei, Tsung-Te Liu
A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm. IEEE J. Solid State Circuits 55 (3) (2020)
Ling-Yu Yeh, Po-Jen Chen, Chen-Chun Pai, Tsung-Te Liu
An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Ting Wang, Tsung-Te Liu
ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm. APCCAS (2020)
Chen-Hsuan Lu, Ying-Tuan Hsu, Bing-Chen Wu, Tsung-Te Liu
Control in 28-nm CMOS. IEEE Trans. Circuits Syst. (12) (2020)
Cheng-Yao Hong, Tsung-Te Liu
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS. IEEE J. Solid State Circuits 55 (8) (2020)
Shang-Yuan Chang, Bing-Chen Wu, Yi-Long Liou, Rui-Xuan Zheng, Pei-Lin Lee, Tzi-Dar Chiueh, Tsung-Te Liu
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Bing-Chen Wu, Tsung-Te Liu
Variation-Resilient Design Techniques for Energy-Constrained Systems. IOLTS (2019)
Chia-Yuan Ku, Tsung-Te Liu
A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Fu-Yan Xie, Bing-Chen Wu, Tsung-Te Liu
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Bing-Chen Wu, Tsung-Te Liu
Circuit Sensing Techniques in Magnetoresistive Random-Access Memory. J. Low Power Electron. 14 (2) (2018)
Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. VLSI-DAT (2017)
Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2016)
Che-Min Huang, Tsung-Te Liu, Tzi-Dar Chiueh
An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction. VLSI-DAT (2015)
Tsung-Te Liu, Jan M. Rabaey
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression. IEEE J. Solid State Circuits 48 (4) (2013)
Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC (2013)
Tsung-Te Liu, Jan M. Rabaey
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression. VLSIC (2012)
Tsung-Te Liu, Jan M. Rabaey
Statistical Analysis and Optimization of Asynchronous Digital Circuits. ASYNC (2012)
Jesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey
Active RFID: Perpetual wireless communications platform for sensors. ESSCIRC (2012)
Tsung-Te Liu, Jan M. Rabaey
Linearity analysis of CMOS passive mixer. ISCAS (2011)
Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey
A low-leakage parallel CRC generator for ultra-low power applications. ISCAS (2011)
Dejan Markovic, Cheng C. Wang, Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey
Ultralow-Power Design in Near-Threshold Region. Proc. IEEE 98 (2) (2010)
Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic. IEEE Trans. Very Large Scale Integr. Syst. 17 (7) (2009)
Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic. ASYNC (2008)
Louis P. Alarcón, Tsung-Te Liu, Matthew D. Pierson, Jan M. Rabaey
Exploring Very Low-Energy Logic: A Case Study. J. Low Power Electron. 3 (3) (2007)
Tsung-Te Liu, Chorng-Kuang Wang
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator. ESSCIRC (2004)