A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator.

Tsung-Te Liu Chorng-Kuang Wang

Published in: ESSCIRC (2004)

Keyphrases

power consumption
high speed
low power
circuit design
mixed signal
feedback loop
clock frequency
learning phase
data conversion
hd video
real time
vlsi architecture