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Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits.
Tsai-Chieh Chen
Chia-Cheng Pai
Yi-Zhan Hsieh
Hsiao-Yin Tseng
Chien-Mo James Li
Tsung-Te Liu
I-Wei Chiu
Published in:
J. Electron. Test. (2021)
Keyphrases
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asynchronous circuits
high speed
delay insensitive
frequency domain
process algebra
discrete fourier transform
model checking
low power
real time
similarity measure
dual formulation
information systems
knowledge base
artificial intelligence
primal dual
genetic algorithm
databases