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Ding-Yuan Lee
ORCID
Publication Activity (10 Years)
Years Active: 2015-2019
Publications (10 Years): 6
Top Topics
Logic Circuits
Single Chip
Content Addressable Memory
Join Processing
Top Venues
VLSI-DAT
IEEE Trans. Circuits Syst. I Regul. Pap.
IEEE/ACM Trans. Netw.
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Chung-An Shen
,
Ding-Yuan Lee
,
Chung-An Ku
,
Meng-Wei Lin
,
Kuo-Cheng Lu
,
Shao-Yu Tan
A Programmable and FPGA-accelerated GTP Offloading Engine for Mobile Edge Computing in 5G Networks.
INFOCOM Workshops
(2019)
Ding-Yuan Lee
,
Ching-Che Wang
,
An-Yeu Wu
Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor.
IEEE Trans. Very Large Scale Integr. Syst.
27 (6) (2019)
Sheng-Chun Kao
,
Ding-Yuan Lee
,
Ting-Sheng Chen
,
An-Yeu Wu
Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing.
IEEE/ACM Trans. Netw.
26 (2) (2018)
Chia-Heng Wu
,
Ting-Sheng Chen
,
Ding-Yuan Lee
,
Tsung-Te Liu
,
An-Yeu Wu
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine.
VLSI-DAT
(2017)
Ting-Sheng Chen
,
Ding-Yuan Lee
,
Tsung-Te Liu
,
An-Yeu Wu
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
(10) (2016)
Huai-Ting Li
,
Ding-Yuan Lee
,
Kun-Chih Chen
,
An-Yeu Andy Wu
An algorithmic error-resilient scheme for robust LDPC decoding.
VLSI-DAT
(2015)