A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS.
Cheng-Yao HongTsung-Te LiuPublished in: IEEE J. Solid State Circuits (2020)
Keyphrases
- error detection and correction
- silicon on insulator
- circuit design
- high speed
- error correction
- cmos technology
- data transmission
- ibm power processor
- low cost
- real time
- design methodology
- nm technology
- metal oxide semiconductor
- asynchronous circuits
- data mining
- encryption algorithm
- low power
- power consumption
- data processing