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Challenges and targets of MRAM-enabled scaled spintronic logic circuits.

F. MengFlorin CiubotaruS.-Y. LeeOdysseas ZografosM. GuptaV. D. NguyenS. CouetGouri Sankar KarGiovanni De MicheliChristoph AdelmannI. Asselberghs
Published in: CoRR (2022)
Keyphrases
  • logic circuits
  • low power
  • design considerations
  • tunnel diode
  • functional decomposition
  • gate array
  • logic synthesis