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Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.
Rongmei Chen
Giuliano Sisto
Odysseas Zografos
Dragomir Milojevic
Pieter Weckx
Geert Van der Plas
Eric Beyne
Published in:
SLIP (2022)
Keyphrases
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invited paper
ibm power processor
low cost
chip design
high speed
multithreading
power consumption
high density
power management
integrity constraints
massively parallel
machine learning
artificial intelligence
expert systems
single chip
power dissipation