Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso A. Jourdain D. Radisic R. Chen G. Arutchelvan B. O'Sullivan Hiroaki Arimura Michele Stucchi An De Keersgieter M. Hosseini T. Hopf K. D'Have S. Wang E. Dupuy G. Mannaert Kevin Vandersmissen S. Iacovo P. Marien S. Choudhury F. Schleicher F. Sebaai Y. Oniki X. Zhou A. Gupta Tom Schram B. Briggs C. Lorant E. Rosseel Andriy Hikavyy Roger Loo J. Geypen D. Batuk G. T. Martinez J. P. Soulie Katia Devriendt B. T. Chan S. Demuynck Gaspard Hiblot Geert Van der Plas Julien Ryckaert Gerald Beyer E. Dentoni Litta Eric Beyne Naoto Horiguchi

Published in: VLSI Technology and Circuits (2022)

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