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A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Jin Guo
Antonis Papanikolaou
Michele Stucchi
Kristof Croes
Zsolt Tokei
Francky Catthoor
Published in:
ACM Great Lakes Symposium on VLSI (2008)
Keyphrases
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high speed
software tools
failure rate
real time
artificial intelligence
higher level
image processing
case study
multiscale
cellular automata
flow field
low power