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Jie Chen
ORCID
Publication Activity (10 Years)
Years Active: 2020-2023
Publications (10 Years): 6
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CoRR
ISSCC
DATE
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Jie Chen
,
Igor Loi
,
Eric Flamand
,
Giuseppe Tagliavini
,
Luca Benini
,
Davide Rossi
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters.
CoRR
(2023)
Jie Chen
,
Igor Loi
,
Eric Flamand
,
Giuseppe Tagliavini
,
Luca Benini
,
Davide Rossi
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters.
IEEE Trans. Very Large Scale Integr. Syst.
31 (4) (2023)
Davide Rossi
,
Francesco Conti
,
Manuel Eggimann
,
Alfio Di Mauro
,
Giuseppe Tagliavini
,
Stefan Mach
,
Marco Guermandi
,
Antonio Pullini
,
Igor Loi
,
Jie Chen
,
Eric Flamand
,
Luca Benini
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits
57 (1) (2022)
Davide Rossi
,
Francesco Conti
,
Manuel Eggimann
,
Stefan Mach
,
Alfio Di Mauro
,
Marco Guermandi
,
Giuseppe Tagliavini
,
Antonio Pullini
,
Igor Loi
,
Jie Chen
,
Eric Flamand
,
Luca Benini
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
ISSCC
(2021)
Davide Rossi
,
Francesco Conti
,
Manuel Eggimann
,
Alfio Di Mauro
,
Giuseppe Tagliavini
,
Stefan Mach
,
Marco Guermandi
,
Antonio Pullini
,
Igor Loi
,
Jie Chen
,
Eric Flamand
,
Luca Benini
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR
(2021)
Jie Chen
,
Igor Loi
,
Luca Benini
,
Davide Rossi
Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster.
DATE
(2020)