Giuseppe Tagliavini

ORCID

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 68

Top Venues

CoRR

DATE

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Parallel Distributed Syst.

University of Bologna, Italy (PHD)

Education History

University of Bologna, Italy

PHD

Publications

Andrea Amidei, Pierangelo Maria Rapa, Giuseppe Tagliavini, Roberto Rabbeni, Paolo Pavan, Simone Benatti
ANGELS - Smart Steering Wheel for Driver Safety. IWASI (2023)
Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, Dimitrios Stathis, Ahmed Hemani
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS (2023)
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (6) (2023)
Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, Andrea Acquaviva
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). PARMA-DITAM (2023)
Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. DATE (2023)
Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors. ACM Trans. Embed. Comput. Syst. 22 (3) (2023)
Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. DATE (2023)
Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. CoRR (2023)
Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Seyed Ahmad Mirsalari, Giuseppe Tagliavini, Davide Rossi, Luca Benini
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. DATE (2023)
Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. CoRR (2022)
Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. CoRR (2022)
Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. IEEE Trans. Parallel Distributed Syst. 33 (5) (2022)
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits 57 (1) (2022)
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. CoRR (2022)
Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. CoRR (2022)
Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning. SAMOS (2022)
Benedetta Mazzoni, Giuseppe Tagliavini, Luca Benini, Simone Benatti
An Optimized Heart Rate Detection System Based on Low-Power Microcontroller Platforms for Biosignal Processing. SYSINT (2022)
Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. AICAS (2022)
Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. CoRR (2022)
Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Fabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini
Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. ARCS (2021)
Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang, Enrico Tabanelli, Giuseppe Tagliavini, Philippe Ryvlin, Luca Benini, Simone Benatti
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. CoRR (2021)
Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang, Enrico Tabanelli, Giuseppe Tagliavini, Philippe Ryvlin, Luca Benini, Simone Benatti
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. BioCAS (2021)
Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ICCD (2021)
Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. IEEE Trans. Computers 70 (8) (2021)
Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. IEEE Trans. Parallel Distributed Syst. 32 (3) (2021)
Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. SAMOS (2021)
Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. DATE (2021)
Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. ESSCIRC (2021)
Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC (2021)
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. IEEE Trans. Emerg. Top. Comput. 9 (3) (2021)
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR (2021)
Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors. CoRR (2021)
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ARITH (2021)
Benedetta Mazzoni, Simone Benatti, Luca Benini, Giuseppe Tagliavini
Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes. IEEE Embed. Syst. Lett. 13 (4) (2021)
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. DATE (2020)
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ISVLSI (2020)
Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. CoRR (2020)
Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi, Luca Benini, Michela Milano
Combining learning and optimization for transprecision computing. CF (2020)
Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
FlexFloat: A Software Library for Transprecision Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices. CoRR (2020)
Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. CoRR (2020)
Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE (2020)
Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
A transprecision floating-point cluster for efficient near-sensor data analytics. CoRR (2020)
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. CoRR (2020)
Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi, Luca Benini, Michela Milano
Combining Learning and Optimization for Transprecision Computing. CoRR (2020)
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. CoRR (2020)
Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. CoRR (2020)
Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
Enabling mixed-precision quantized neural networks in extreme-edge devices. CF (2020)
Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA. DATE (2019)
Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits 54 (7) (2019)
Victor Javier Kartsch, Giuseppe Tagliavini, Marco Guermandi, Simone Benatti, Davide Rossi, Luca Benini
BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity. IEEE Trans. Biomed. Circuits Syst. 13 (5) (2019)
Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators. J. Real Time Image Process. 15 (1) (2018)
Giuseppe Tagliavini, Davide Rossi, Andrea Marongiu, Luca Benini
Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing. ISCAS (2018)
A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew Emerson, Andrés Tomás, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn
The transprecision computing paradigm: Concept, design, and applications. DATE (2018)
Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
A transprecision floating-point platform for ultra-low power computing. DATE (2018)
Giuseppe Tagliavini, Daniele Cesarini, Andrea Marongiu
Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking. IEEE Trans. Parallel Distributed Syst. 29 (9) (2018)
Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
A Transprecision Floating-Point Platform for Ultra-Low Power Computing. CoRR (2017)
Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
Enabling OpenVX support in mW-scale parallel accelerators. CASES (2016)
Giuseppe Tagliavini, Andrea Marongiu, Davide Rossi, Luca Benini
Always-on motion detection with application-level error control on a near-threshold approximate computing platform. ICECS (2016)
Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium (2015)
Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
A framework for optimizing OpenVX applications performance on embedded manycore accelerators. SCOPES (2015)
Nandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini
Exploring architectural heterogeneity in intelligent vision systems. HPCA (2015)
Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators. MCSoC (2015)
Andrea Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, Luca Benini
Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives. IEEE Trans. Ind. Informatics 11 (4) (2015)
Giuseppe Tagliavini, Davide Rossi, Luca Benini, Andrea Marongiu
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. ISVLSI (2015)
Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters. DATE (2014)
Giuseppe Tagliavini, Germain Haugou, Luca Benini
Supporting localized OpenVX kernel execution for efficient computer vision application development on STHORM many-core platform. Conf. Computing Frontiers (2014)
Giuseppe Tagliavini, Germain Haugou, Luca Benini
Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators. DASIP (2014)
Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters. DATE (2013)
Andrea Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, Luca Benini
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP. MES (2013)
Alessio Franceschelli, Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Martino Ruggiero, Michele Lombardi, Alessio Bonfietti, Michela Milano, Luca Benini
MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor. Conf. Computing Frontiers (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Giuseppe Tagliavini