Ahmed Hemani

ORCID

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 52

Top Venues

CoRR

DSD

Microprocess. Microsystems

SAMOS

Publications

Haider Abbas, Muhammad Shahzad, Maliha Safdar, Ahmed Hemani
DUDE: Decryption, Unpacking, Deobfuscation, and Endian Conversion Framework for Embedded Devices Firmware. IEEE Trans. Dependable Secur. Comput. 21 (4) (2024)
Deyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou
FPGA-Based HPC for Associative Memory System. ASPDAC (2024)
Yu Yang, Jordi Altayó González, Ahmed Hemani
CIS: Composable Instruction Set for Streaming Applications: Design, Modeling, and Scheduling. CoRR (2024)
Jiawei Xu, Yi Zheng, Feng Li, Dimitrios Stathis, Ruisi Shen, Haoming Chu, Anders Lansner, Lirong Zheng, Zhuo Zou, Ahmed Hemani
Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 71 (2) (2024)
Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, Dimitrios Stathis, Ahmed Hemani
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS (2023)
Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Chengwei Cao, Dimitrios Stathis, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou
A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning. IEEE Trans. Biomed. Circuits Syst. 17 (5) (2023)
Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani
Implementation of Image Averaging on DRRA and DiMArch Architectures. SBCCI (2023)
Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani
DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID (2023)
Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
Clock tree generation by abutment in synchoros VLSI design. Microprocess. Microsystems 102 (2023)
Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani
Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. HEART (2023)
Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani
Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. DSD (2023)
Jiawei Xu, Yi Zheng, Chenxu Sheng, Yichen Cai, Dimitrios Stathis, Ruisi Shen, Lirong Zheng, Zhuo Zou, Laigui Hu, Ahmed Hemani
Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks. NEWCAS (2023)
Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani
MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks. J. Syst. Archit. 133 (2022)
Yu Yang, Dimitrios Stathis, Ahmed Hemani
Reducing the Configuration Overhead of the Distributed Two-level Control System. DATE (2022)
Yu Yang, Ahmed Hemani
Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style. CoRR (2022)
Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Yuning Wang, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou
Memristor-Based In-Circuit Computation for Trace-Based STDP. AICAS (2022)
Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design. CoRR (2021)
Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
Synthesis of predictable global NoC by abutment in synchoros VLSI design. NOCS (2021)
Yu Yang, Ahmed Hemani, Kolin Paul
Scheduling Persistent and Fully Cooperative Instructions. FCCM (2021)
Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani
Design and Implementation of Optimized Register File for Streaming Applications. VDAT (2021)
Syed Mohammad Asad Hassan Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. ACM Trans. Archit. Code Optim. 18 (1) (2021)
Yu Yang, Ahmed Hemani, Kolin Paul
Scheduling Persistent and Fully Cooperative Instructions. DSD (2021)
Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
Clock Tree Generation by Abutment in Synchoros VLSI Design. NorCAS (2021)
Dimitrios Stathis, Yu Yang, Ahmed Hemani, Anders Lansner
Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. DATE (2021)
Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani
Multi-objective Recurrent Neural Networks Optimization for the Edge - a Quantization-based Approach. CoRR (2021)
Jiawei Xu, Deyu Wang, Feng Li, Lianhao Zhang, Dimitrios Stathis, Yu Yang, Yi Jin, Anders Lansner, Ahmed Hemani, Zhuo Zou, Li-Rong Zheng
A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. AICAS (2021)
Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. 92 (11) (2020)
Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, Maurizio Martina
NACU: A Non-Linear Arithmetic Unit for Neural Networks. DAC (2020)
Ahmed Hemani, Muhammad Shafique, Kolin Paul
Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks. J. Signal Process. Syst. 92 (11) (2020)
Lizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng
A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network. NorCAS (2020)
Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. CoRR (2019)
Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR (2019)
Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred Grabherr, Rafi Ahmad
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. ISVLSI (2019)
Muhammad Ali Shami, Muhammad Adeel Tajammul, Ahmed Hemani
Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays. J. Signal Process. Syst. 91 (5) (2019)
Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. CoRR (2019)
Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred Grabherr, Rafi Ahmad
RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. SAMOS (2018)
Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn
3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Int. J. Parallel Program. 45 (6) (2017)
Y. Yang, Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs. PARMA-DITAM@HiPEAC (2017)
Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
Can a reconfigurable architecture beat ASIC as a CNN accelerator? SAMOS (2017)
Ahmed Hemani, Syed Mohammad Asad Hassan Jafri, Shayesteh Masoumian
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable. NOCS (2017)
Syed Mohammad Asad Hassan Jafri, Nasim Farahini, Ahmed Hemani
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level. ISVLSI (2017)
Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Leonardo Intesa
SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs. DSD (2017)
Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Naeem Abbas
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. IPDPS (2017)
Mohammad Badawi, Zhonghai Lu, Ahmed Hemani
Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture. Microprocess. Microsystems 54 (2017)
Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. J. Signal Process. Syst. 87 (3) (2017)
Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. PATMOS (2016)
Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen
Polymorphic Configuration Architecture for CGRAs. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Mohammad Badawi, Zhonghai Lu, Ahmed Hemani
Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture. DSD (2016)
Mohammad Badawi, Zhonghai Lu, Ahmed Hemani
Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture. PDP (2016)
Syed M. A. H. Jafri, Masoud Daneshtalab, Naeem Abbas, Guillermo Serrano Leon, Ahmed Hemani
TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs. IEEE Trans. Computers 65 (11) (2016)
Jamshaid Sarwar Malik, Ahmed Hemani
Gaussian Random Number Generation: A Survey on Hardware Architectures. ACM Comput. Surv. 49 (3) (2016)
Ahmed Hemani
The SiLago Method: Next Generation VLSI Architectures and Design Methods. MES@ISCA (2016)
Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen, Juha Plosila
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. VLSI Design (2015)
Jamshaid Sarwar Malik, Ahmed Hemani, Jameel Nawaz Malik, Ben Slimane, Nasirud Din Gohar
Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Naeem Abbas, Muhammad Ali Awan, Juha Plosila
TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. Microprocess. Microsystems 39 (8) (2015)
Nasim Farahini, Ahmed Hemani
Atomic stream computation unit based on micro-thread level parallelism. ASAP (2015)
Syed M. A. H. Jafri, Ozan Ozbag, Nasim Farahini, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. ACM J. Emerg. Technol. Comput. Syst. 11 (4) (2015)
Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Shuo Li
Physical design aware system level synthesis of hardware. SAMOS (2015)
Tuan Ngyen, Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Sergei Dytckov, Juha Plosila, Hannu Tenhunen
FIST: A Framework to Interleave Spiking Neural Networks on CGRAs. PDP (2015)
Pei Liu, Ahmed Hemani, Kolin Paul
3D-stacked many-core architecture for biological sequence analysis problems. SAMOS (2015)
Anders Lansner, Ahmed Hemani, Nasim Farahini
Spiking brain models: Computation, memory and communication constraints for custom hardware implementation. ASP-DAC (2014)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18 (3-4) (2014)
Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen
Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD (2014)
Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsystems 38 (8) (2014)
Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen
Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM (2014)
Shuo Li, Ahmed Hemani
Three-Dimensional Design Space Exploration for System Level Synthesis. DSD (2014)
Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
TransPar: Transformation based dynamic Parallelism for low power CGRAs. FPL (2014)
Hassan Anwar, Syed M. A. H. Jafri, Sergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Ahmed Hemani, Juha Plosila, Giovanni Beltrame, Hannu Tenhunen
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures. MES (2014)
Syed M. A. H. Jafri, Tuan Nguyen Gia, Sergei Dytckov, Masoud Daneshtalab, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
NeuroCGRA: A CGRA with support for neural networks. HPCS (2014)
Jean-Michel Chabloz, Ahmed Hemani
Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Mohammad Badawi, Ahmed Hemani, Zhonghai Lu
Customizable coarse-grained energy-efficient reconfigurable packet processing architecture. ASAP (2014)
Shuo Li, Ahmed Hemani
Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver. FCCM (2014)
Siavoosh Payandeh Azad, Nasim Farahini, Ahmed Hemani
Customization methodology of a Coarse Grained Reconfigurable architecture. NORCHIP (2014)
Pei Liu, Ahmed Hemani, Kolin Paul
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. ISSoC (2014)
Nasim Farahini, Ahmed Hemani, Anders Lansner, Fabien Clermidy, Christer Svensson
A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. ASP-DAC (2014)
Shuo Li, Ahmed Hemani
Case Study: Constraint Programming in a System Level Synthesis Framework. CP (2014)
Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. ICSAMOS (2014)
Masoud Daneshtalab, Maurizio Palesi, Juha Plosila, Ahmed Hemani
Special issue on many-core embedded systems. Microprocess. Microsystems 38 (6) (2014)
Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED (2013)
Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocess. Microsystems 37 (8-A) (2013)
Shuo Li, Nasim Farahini, Ahmed Hemani, Kathrin Rosvall, Ingo Sander
System level synthesis of hardware for DSP applications using pre-characterized function implementations. CODES+ISSS (2013)
Shuo Li, Ahmed Hemani
Memory allocation and optimization in system-level architectural synthesis. ReCoSoC (2013)
Iraklis Anagnostopoulos, Jean-Michel Chabloz, Ioannis Koutras, Alexandros Bartzas, Ahmed Hemani, Dimitrios Soudris
Power-aware dynamic memory management on many-core platforms utilizing DVFS. ACM Trans. Embed. Comput. Syst. 13 (1s) (2013)
Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
Private configuration environments (PCE) for efficient reconfiguration, in CGRAs. ASAP (2013)
Shuo Li, Jamshaid Sarwar Malik, Shaoteng Liu, Ahmed Hemani
A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. MES (2013)
Shuo Li, Nasim Farahini, Ahmed Hemani
Global Control and Storage Synthesis for a System Level Synthesis Approach. FCCM (2013)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD (2013)
Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. ICSAMOS (2013)
Nasim Farahini, Ahmed Hemani, Kolin Paul
Distributed Runtime Computation of Constraints for Multiple Inner Loops. DSD (2013)
Jamshaid Sarwar Malik, Ahmed Hemani, Nasirud Din Gohar
Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator. ASAP (2013)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC (2013)
U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar
High performance 3D-FFT implementation. ISCAS (2013)
Nasim Farahini, Shuo Li, Muhammad Adeel Tajammul, Muhammad Ali Shami, Guo Chen, Ahmed Hemani, Wei Ye
39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation. ISCAS (2013)
Shuo Li, Ahmed Hemani
Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework. DSD (2013)
Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS (2012)
Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani
Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture. MCSoC (2012)
Pei Liu, Ahmed Hemani, Kolin Paul
Improved Bioinformatics Processing Unit for Multiple Applications. IPDPS Workshops (2012)
Jean-Michel Chabloz, Ahmed Hemani
Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links. VLSI Design (2012)
Muhammad Ali Shami, Ahmed Hemani
Classification of Massively Parallel Computer Architectures. IPDPS Workshops (2012)
Jamshaid Sarwar Malik, Paolo Palazzari, Ahmed Hemani
Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question. SIGARCH Comput. Archit. News 40 (5) (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Ahmed Hemani