Srinivas Boppu

ORCID

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 15

Top Venues

MCSoC

VDAT

iSES

ACM Trans. Embed. Comput. Syst.

University of Erlangen-Nuremberg (PHD)

Education History

University of Erlangen-Nuremberg

PHD

Publications

Yalagala Sivanjaneyulu, Srinivas Boppu, M. Sabarimalai Manikandan
Compressive Sensing-Based Automatic PPG Signal Quality Assessment Using CNN for Energy-Constrained Medical Devices. ECAI (2023)
Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. ACM Trans. Design Autom. Electr. Syst. 28 (3) (2023)
Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani
Implementation of Image Averaging on DRRA and DiMArch Architectures. SBCCI (2023)
Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani
DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID (2023)
Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani
Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. HEART (2023)
Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani
Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. DSD (2023)
Ashish Reddy Bommana, Srinivas Boppu
A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization. MCSoC (2022)
Chakkapalli Manikanta Suryateja, Srinivas Boppu, Linga Reddy Cenkeramaddi, Barathram Ramkumar
Hand Gesture Recognition System in the Complex Background for Edge Computing Devices. iSES (2022)
Susheel Ujwal Siddamshetty, Suresh Nambi, Srinivas Boppu, Debapratim Ghosh
Efficient Multiplication and Accumulation of Signed Numbers. iSES (2022)
Pudi Dhilleswararao, Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi
Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey. IEEE Access 10 (2022)
Susheel Ujwal Siddamshetty, Srinivas Boppu, Debapratim Ghosh
Efficient Hardware Architecture for Posit Addition/Subtraction. MCSoC (2022)
Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani
Design and Implementation of Optimized Register File for Streaming Applications. VDAT (2021)
T. K. R. Arvind, Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT (2020)
Kinjarapu Manojkumar, Srinivas Boppu, M. Sabarimalai Manikandan
An Automated Algorithm for Estimating Respiration Rate from PPG Signals. MIND (2) (2020)
Spandan Dey, Srinivas Boppu, M. Sabarimalai Manikandan
Design of a Real-Time Automatic Source Monitoring Framework Based on Sound Source Localization. ICDIPC (2019)
Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13 (4s) (2014)
Srinivas Boppu, Frank Hannig, Jürgen Teich
Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. 77 (1-2) (2014)
Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich
System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers (2013)
Srinivas Boppu, Frank Hannig, Jürgen Teich
Loop program mapping and compact code generation for programmable hardware accelerators. ASAP (2013)
Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich
A prototype of an invasive tightly-coupled processor array. DASIP (2012)
Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich
Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich
Design of Low Power On-chip Processor Arrays. ASAP (2012)
Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig (2011)

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Publication Activity (10 Years)

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Srinivas Boppu