Vahid Lari

Publication Activity (10 Years)

Years Active: 2007-2017
Publications (10 Years): 2

Top Venues

ASAP

J. Syst. Archit.

AHS

DASIP

University of Erlangen-Nuremberg, Germany (PHD)

Education History

University of Erlangen-Nuremberg, Germany

PHD

Publications

Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers 66 (3) (2017)
Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
Providing fault tolerance through invasive computing. it Inf. Technol. 58 (6) (2016)
Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting
Adaptive fault tolerance through invasive computing. AHS (2015)
Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61 (10) (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP (2015)
Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61 (10) (2015)
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS (2015)
Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
Massively Parallel Processor Architectures for Resource-aware Computing. CoRR (2014)
Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13 (4s) (2014)
Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC (2014)
Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP (2014)
Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich
System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers (2013)
Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO (2013)
Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich
A prototype of an invasive tightly-coupled processor array. DASIP (2012)
Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich
Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich
Design of Low Power On-chip Processor Arrays. ASAP (2012)
Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
Invasive manycore architectures. ASP-DAC (2012)
Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich
Decentralized dynamic resource management support for massively parallel processor arrays. ASAP (2011)
Vahid Lari, Frank Hannig, Jürgen Teich
Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops (2011)
Vahid Lari, Frank Hannig, Jürgen Teich
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops (2009)
Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi
Fault Effects in FlexRay-Based Networks with Hybrid Topology. ARES (2008)
Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand
Assessment of Message Missing Failures in FlexRay-Based Networks. PRDC (2007)

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Publication Activity (10 Years)

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Vahid Lari