Alexandru Tanase

Publication Activity (10 Years)

Years Active: 2013-2021
Publications (10 Years): 15

Top Venues

ASAP

ACM Trans. Embed. Comput. Syst.

ReConFig

MEMOCODE

University of Erlangen-Nuremberg, Germany (PHD)

Education History

University of Erlangen-Nuremberg, Germany

PHD

Publications

Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33 (14) (2021)
Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP (2018)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig (2017)
Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC (2017)
Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89 (2) (2017)
Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig (2017)
Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
Efficiency in ILP processing by using orthogonality. ASAP (2017)
Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP (2016)
Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
Providing fault tolerance through invasive computing. it Inf. Technol. 58 (6) (2016)
Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting
Adaptive fault tolerance through invasive computing. AHS (2015)
Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61 (10) (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP (2015)
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE (2014)
Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal
Domain-specific augmentations for High-Level Synthesis. ASAP (2014)
Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
Massively Parallel Processor Architectures for Resource-aware Computing. CoRR (2014)
Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13 (4s) (2014)
Jürgen Teich, Alexandru Tanase, Frank Hannig
Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. 77 (1-2) (2014)
Jürgen Teich, Alexandru Tanase, Frank Hannig
Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP (2013)
Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP (2013)
Moritz Schmid, Frank Hannig, Alexandru Tanase, Jürgen Teich
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO (2013)
Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO (2013)
Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP (2013)

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Publication Activity (10 Years)

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Alexandru Tanase