Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.
Alexandru TanaseMichael WitteraufJürgen TeichFrank HannigPublished in: MEMOCODE (2015)
Keyphrases
- memory access
- shared memory
- main memory
- database workloads
- external memory
- parallel processing
- cache misses
- distributed memory
- secondary storage
- memory management
- disk accesses
- inter processor communication
- ibm zenterprise
- instruction set
- memory hierarchy
- memory subsystem
- virtual memory
- input output
- data access
- direct memory access
- parallel algorithm
- access patterns
- random access memory
- multiprocessor systems
- garbage collection
- address space
- internal memory
- message passing
- level parallelism
- index structure
- data structure
- memory space
- processor core
- multi core systems
- intel xeon
- multithreading
- read write
- computational power
- database management systems
- shared memory multiprocessors
- parallel computing
- data transfer
- parallel architecture
- data partitioning
- parallel architectures
- ibm eservertm
- operating system
- file system
- ibm power processor
- memory efficient
- cache conscious
- memory bandwidth
- disk access
- computing power
- parallel programming
- storage devices
- prefetching
- memory requirements
- random access
- processing units