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Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction.

Ashish Reddy BommanaSusheel Ujwal SiddamshettyPudi DhilleswararaoArvind Thumatti K. R.Srinivas BoppuM. Sabarimalai ManikandanLinga Reddy Cenkeramaddi
Published in: ACM Trans. Design Autom. Electr. Syst. (2023)
Keyphrases
  • floating point
  • floating point arithmetic
  • instruction set
  • embedded systems
  • fixed point
  • square root
  • design process
  • interval arithmetic
  • pairwise
  • low cost
  • hardware design
  • sparse matrices