Can a reconfigurable architecture beat ASIC as a CNN accelerator?
Syed M. A. H. JafriAhmed HemaniDimitrios StathisPublished in: SAMOS (2017)
Keyphrases
- reconfigurable architecture
- cellular neural networks
- integrated circuit
- systolic array
- hardware implementation
- field programmable gate array
- convolutional neural network
- hardware architecture
- application specific
- design methodology
- parallel implementation
- single chip
- physical design
- compute intensive
- circuit design
- beat classification
- centroid neural network
- fixed point
- parallel architecture
- parallel computing
- case study
- parallel processing
- signal processing
- low cost
- higher order
- general purpose
- database systems