A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture.
Pei LiuAhmed HemaniKolin PaulPublished in: ISSoC (2014)
Keyphrases
- parallel architecture
- distributed memory
- shared memory
- multithreading
- hardware implementation
- fine grain
- parallel implementation
- multiprocessor systems
- real time
- scientific computing
- parallel processing
- reconfigurable hardware
- client server architecture
- parallel computers
- multi processor
- cross platform
- ibm sp
- computing platform
- communication protocol
- data parallelism
- parallel algorithm
- java platform
- parallel machines
- central processor
- abstraction layer
- hardware architecture
- matrix multiplication
- hardware software
- multi core processors
- parallel architectures
- processing units
- parallel computing
- computational complexity