Thomas Christoph Müller

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 10

Top Topics

Hardware Implementation

Low Density Parity Check

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Simone Machetti, Pasquale Davide Schiavone, Thomas Christoph Müller, Miguel Peón Quirós, David Atienza
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators. CoRR (2024)
Pasquale Davide Schiavone, Simone Machetti, Miguel Peón Quirós, Jose Miranda, Benoît W. Denkinger, Thomas Christoph Müller, Ruben Rodríguez, Saverio Nasturzio, David Atienza Alonso
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller. CF (2023)
Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (4) (2017)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code. CoRR (2017)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR (2017)
Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. CoRR (2017)
Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test 34 (6) (2017)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
A multi-Gbps unrolled hardware list decoder for a systematic polar code. ACSSC (2016)
Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC (2016)