Claude Thibeault

ORCID

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 28

Top Venues

CoRR

VTS

NEWCAS

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Simon Pichette, Claude Thibeault
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (7) (2023)
Mickaël Fiorentino, Claude Thibeault, Yvon Savaria
Introducing KeyRing self-timed microarchitecture and timing-driven design flow. IET Comput. Digit. Tech. 15 (6) (2021)
Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Mickaël Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey, Michel Laurence
AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology. ASYNC (2019)
Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. J. Electron. Test. 35 (6) (2019)
Maryem Benyoussef, Claude Thibeault, Yvon Savaria
A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. ISCAS (2019)
Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault
Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. VTS (2018)
Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross
Low-Latency Software Polar Decoders. J. Signal Process. Syst. 90 (5) (2018)
Pascal Giard, Alexios Balatsoukas-Stimming, Gabi Sarkis, Claude Thibeault, Warren J. Gross
Fast Low-Complexity Decoders for Low-Rate Polar Codes. J. Signal Process. Syst. 90 (5) (2018)
Claude Thibeault, Ghyslain Gagnon
On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (4) (2017)
Mickaël Fiorentino, Yvon Savaria, Claude Thibeault
FPGA implementation of Token-based Self-timed processors: A case study. NEWCAS (2017)
Claude Thibeault, Ali Louati
A new delay testing signal scheme robust to power distribution network impedance variation. VTS (2017)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code. CoRR (2017)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR (2017)
Azeddine Ghodbane, Maarouf Saad, Christelle Hobeika, Jean-François Boland, Claude Thibeault
Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays. IEEE Trans. Aerosp. Electron. Syst. 52 (2) (2016)
Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
Towards an efficient SEU effects emulation on SRAM-based FPGAs. Microelectron. Reliab. 66 (2016)
Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross
Hardware Decoders for Polar Codes: An Overview. CoRR (2016)
Pascal Giard, Alexios Balatsoukas-Stimming, Gabi Sarkis, Claude Thibeault, Warren J. Gross
Fast Low-Complexity Decoders for Low-Rate Polar Codes. CoRR (2016)
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
A multi-Gbps unrolled hardware list decoder for a systematic polar code. ACSSC (2016)
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
Multi-Mode Unrolled Architectures for Polar Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2016)
Mickaël Fiorentino, Yvon Savaria, Claude Thibeault, Pascal Gervais
A practical design method for prototyping self-timed processors using FPGAs. ISCAS (2016)
Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria
Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA. CCECE (2016)
Gabi Sarkis, Ido Tal, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. IEEE Trans. Commun. 64 (7) (2016)
Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
Hardware decoders for polar codes: An overview. ISCAS (2016)
Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Fast List Decoders for Polar Codes. IEEE J. Sel. Areas Commun. 34 (2) (2016)
Seyyed Ali Hashemi, Alexios Balatsoukas-Stimming, Pascal Giard, Claude Thibeault, Warren J. Gross
Partitioned successive-cancellation list decoding of polar codes. ICASSP (2016)
Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
WeSPer: A flexible small delay defect quality metric. VTS (2016)
Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. IOLTS (2015)
Seyyed Ali Hashemi, Alexios Balatsoukas-Stimming, Pascal Giard, Claude Thibeault, Warren J. Gross
Partitioned Successive-Cancellation List Decoding of Polar Codes. CoRR (2015)
Christelle Hobeika, Claude Thibeault, Jean-François Boland
Functional Constraint Extraction From Register Transfer Level for ATPG. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs. SiPS (2015)
Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. EWDTS (2015)
Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross
Low-Latency Software Polar Decoders. CoRR (2015)
Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Unrolled Polar Decoders, Part II: Fast List Decoders. CoRR (2015)
Louis-Charles Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, Thomas Awad, Doug Morrissey
A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline. ASYNC (2015)
Claude Thibeault
Foreword. VTS (2015)
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
Unrolled Polar Decoders, Part I: Hardware Architectures. CoRR (2015)
Mostafa Darvishi, Yves Audet, Yves Blaquière, Claude Thibeault
Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. CoRR (2015)
Mickaël Fiorentino, Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
Self-timed circuits FPGA implementation flow. NEWCAS (2015)
Gabi Sarkis, Ido Tal, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. CoRR (2015)
Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Fast Polar Decoders: Algorithm and Implementation. IEEE J. Sel. Areas Commun. 32 (5) (2014)
Gabi Sarkis, Pascal Giard, Claude Thibeault, Warren J. Gross
Autogenerating software polar decoders. GlobalSIP (2014)
Christelle Hobeika, Simon Pichette, M. A. Leonard, Claude Thibeault, Jean-François Boland, Yves Audet
Multi-abstraction level signature generation and comparison based on radiation single event upset. IOLTS (2014)
Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Increasing the Speed of Polar List Decoders. CoRR (2014)
Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria, Simon Pichette, Yves Audet
On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations. CoRR (2014)
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
Fast software polar decoders. ICASSP (2014)
Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Increasing the speed of polar list decoders. SiPS (2014)
Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria, Claude Thibeault
Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. MEMOCODE (2014)
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
A 237 Gbps Unrolled Hardware Polar Decoder. CoRR (2014)
Christelle Hobeika, Claude Thibeault, Jean-François Boland
Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG. CoRR (2013)
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
A Fast Software Polar Decoder. CoRR (2013)
Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
Fast Polar Decoders: Algorithm and Implementation. CoRR (2013)
Claude Thibeault, Yassine Hariri, Syed Rafay Hasan, Christelle Hobeika, Yvon Savaria, Yves Audet, Fatima Zahra Tazi
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. J. Electron. Test. 29 (4) (2013)
Zakaria El Alaoui Ismaili, Frederic Nabki, Wessam Ajib, Claude Thibeault
A 0.35∼6.25 GHz cognitive radio frequency synthesizer architecture. MWSCAS (2013)
R. Robache, Jean-François Boland, Claude Thibeault, Yvon Savaria
A methodology for system-level fault injection based on gate-level faulty behavior. NEWCAS (2013)
Georges Kaddoum, Francois-Dominique Richardson, Sarra Adouni, François Gagnon, Claude Thibeault
Multi-User Multi-Carrier Differential Chaos Shift Keying Communication System CoRR (2013)
Georges Kaddoum, Francois-Dominique Richardson, Sarra Adouni, François Gagnon, Claude Thibeault
Multi-user Multi-Carrier Differential Chaos Shift Keying communication system. IWCMC (2013)
Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria, Claude Thibeault
Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking. FTSCS (2013)
Azeddine Ghodbane, Maarouf Saad, Jean-François Boland, Claude Thibeault
Fault tolerant flight control system using emmae method and reconfiguration with sliding mode technique. CCECE (2012)
François Leduc-Primeau, Alexandre J. Raymond, Pascal Giard, Kevin Cushon, Claude Thibeault, Warren J. Gross
High-throughput LDPC decoding using the RHS algorithm. DASIP (2012)
Marwen Bouanen, François Gagnon, Georges Kaddoum, Denis Couillard, Claude Thibeault
An LPI design for secure OFDM systems. MILCOM (2012)
Pascal Giard, Georges Kaddoum, François Gagnon, Claude Thibeault
FPGA implementation and evaluation of discrete-time chaotic generators circuits. IECON (2012)
Claude Thibeault, Yassine Hariri, Christelle Hobeika
Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors. J. Electron. Test. 28 (2) (2012)
Claude Thibeault, Yassine Hariri
CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Marc Joliveau, Michel Gendreau, François Gagnon, Claude Thibeault
Low complexity low power non-recursive digital filters with unconstrained topology. ECCTD (2011)
Charles L. Despins, Fabrice Labeau, Tho Le-Ngoc, Richard Labelle, Mohamed Cheriet, Claude Thibeault, François Gagnon, Alberto Leon-Garcia, Omar Cherkaoui, Bill St. Arnaud, Jacques Mcneill, Yves Lemieux, Mathieu Lemay
Leveraging green communications for carbon emission reductions: Techniques, testbeds, and emerging carbon footprint standards. IEEE Commun. Mag. 49 (8) (2011)
Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault
Testing for Parasitic Memory Effect in SRAMs. Asian Test Symposium (2011)
René Gagné, Jean Belzile, Claude Thibeault
From synchronous to GALS: A new architecture for FPGAs. Microelectron. J. 40 (11) (2009)
Yassine Hariri, Claude Thibeault
Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors. IET Comput. Digit. Tech. 1 (6) (2007)
Claude Thibeault
On a New Outlier Rejection Technique. VTS (2007)
Claude Thibeault
On New Current Signatures and Adaptive Test Technique Combination. VTS (2004)
Claude Thibeault
Measurements. J. Electron. Test. 19 (6) (2003)
Yassine Hariri, Claude Thibeault
3DSDM: A 3 Data-Source Diagnostic Method. DFT (2003)
Claude Thibeault
Testing: With Variance Reduction. J. Electron. Test. 19 (3) (2003)
Claude Thibeault
Speeding-Up IDDQ Measurements. VTS (2002)
Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault
Yield Modeling of a WSI Telecom Router Architecture. DFT (2002)
Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst
Tools for the Characterization of Bipolar CML Testability. VTS (2001)
Claude Thibeault
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults. IEEE Trans. Computers 49 (6) (2000)
Claude Thibeault
Improving Delta-I_DDQ-based test methods. ITC (2000)
Claude Thibeault
Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results. J. Electron. Test. 16 (4) (2000)
Claude Thibeault
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. VTS (2000)
Claude Thibeault
An histogram based procedure for current testing of active defects. ITC (1999)
Claude Thibeault
On the Comparison of IDDQ and IDDQ Testing. VTS (1999)
Claude Thibeault, Guy Bégin
A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations. IEEE Trans. Computers 48 (6) (1999)
Claude Thibeault, Luc Boisvert
Diagnosis method based on ΔIddq probabilistic signatures: experimental results. ITC (1998)
Claude Thibeault
Increasing Current Testing Resolution. DFT (1998)
Claude Thibeault, Luc Boisvert
On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. DFT (1998)
Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. DFT (1997)
Claude Thibeault
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. VTS (1997)
Michel Kafrouni, Claude Thibeault, Yvon Savaria
A Cost Model for VLSI / MCM Systems. DFT (1997)
Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
Panel Summaries. IEEE Des. Test Comput. 13 (3) (1996)
Claude Thibeault, A. Payeur
Experimental Results from Iddf Testing. DFT (1996)
Claude Thibeault, Yvon Savaria, Jean-Louis Houle
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. IEEE Trans. Computers 44 (5) (1995)
Claude Thibeault, A. Payeur
FFT-based test of a yield monitor circuit. DFT (1995)
Claude Thibeault
Detection and location of faults and defects using digital signal processing. VTS (1995)
Claude Thibeault
Using Fourier Analysis to Enhance IC Testability. DFT (1994)
Claude Thibeault, Yvon Savaria, Jean-Louis Houle
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. IEEE Trans. Computers 43 (6) (1994)
J. Crépeau, Claude Thibeault, Yvon Savaria
Some Results on Yield and Local Design Rule Relaxation. DFT (1993)
Claude Thibeault, Yvon Savaria, Jean-Louis Houle
Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits. J. Circuits Syst. Comput. 2 (2) (1992)

Claude Thibeault.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Claude Thibeault