A multi-Gbps unrolled hardware list decoder for a systematic polar code.
Pascal GiardAlexios Balatsoukas-StimmingThomas Christoph MüllerAndreas Peter BurgClaude ThibeaultWarren J. GrossPublished in: ACSSC (2016)
Keyphrases
- error detection
- reed solomon
- hardware and software
- low cost
- real time
- massively parallel
- low complexity
- error concealment
- error correction
- rotation invariant
- low density parity check
- fpga implementation
- source code
- image processing
- error control
- industry standard
- ldpc codes
- protection scheme
- motion estimation
- hardware implementation
- fourier transform
- computer systems
- address space