Yves Blaquière

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 30

Top Topics

Pipelined Architecture

Ionizing Radiation

Integrated Circuit

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Allan Riboullet, Frédéric Nabki, Yves Blaquière, Glenn E. R. Cowan
Configurable and Intelligent Switched CMOS Current Driver Powering Arrays of Electrothermal Actuators for MEMS Switches. ISCAS (2024)
Amirhossein Moshrefi, Yves Blaquière, Frederic Nabki
A Precise and Reliable Engine Knock Detection Utilizing Meta Classifier. ISCAS (2024)
Hachem Bensalem, Yves Blaquière, Yvon Savaria
An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Hamid Sadrimanesh, Yves Blaquière, Frederic Nabki
Toward 2.5D Structures for Multi-Channel MEMS Acoustic-Based Digital Isolators using Through Silicon Openings. NEWCAS (2023)
Abdurrashid Hassan Shuaibu, Yves Blaquière, Frédéric Nabki
Toward a Polysilicon-Based Electrostatically Actuated DC MEMS Switch. NEWCAS (2023)
Van Ha Nguyen, Xuan-Dien Do, Yves Blaquière, Glenn E. R. Cowan
Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications. NEWCAS (2022)
Abdurrashid Hassan Shuaibu, Frédéric Nabki, Yves Blaquière
A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience. NEWCAS (2022)
Van Ha Nguyen, Nueraimaiti Aimaier, Gabriel Nobert, Tan Pham, Nicolas G. Constantin, Yves Blaquière, Glenn E. R. Cowan
A Reconfigurable Power System-in-Package Module using GaN HEMTs and IC Bare Dies on LTCC Substrate: Design - Implementation - Experiment and Future Directions. NEWCAS (2022)
Van Ha Nguyen, Xuan-Dien Do, Yves Blaquière, Glenn E. R. Cowan
A 3.3 V 0.1-1 A Hybrid Buck-Boost Converter with 85-97 % Power Efficiency Range Highly-Suited for Battery-Powered Devices using Low-Profile High-DCR Inductor. NEWCAS (2022)
Gabriel Nobert, Abdul Hafiz Alameh, Nam Ly, Nicolas G. Constantin, Yves Blaquière
Towards an LTCC SiP for Control System in Safety-Critical Applications. ISCAS (2021)
Nueraimaiti Aimaier, Nam Ly, Gabriel Nobert, Yves Blaquière, Nicolas G. Constantin, Glenn E. R. Cowan
SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit. ISCAS (2021)
Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan
Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-Iq All-in-One Bandgap Comparator. ISCAS (2021)
Safa Berrima, Yves Blaquière, Yvon Savaria
Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Trans. Instrum. Meas. 70 (2021)
Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan
A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Van Ha Nguyen, Abdul Hafiz Alameh, Nam Ly, Yves Blaquière, Glenn E. R. Cowan
A Novel Minimum-Phase Dual-Inductor Hybrid Boost Converter with PWM Voltage-Mode Controller. ISCAS (2021)
Hachem Bensalem, Yves Blaquière, Yvon Savaria
Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. ISCAS (2021)
Safa Berrima, Yves Blaquière, Yvon Savaria
Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices Syst. 14 (8) (2020)
Nam Ly, Nueraimaiti Aimaier, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan, Nicolas G. Constantin
A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology. NEWCAS (2020)
Hachem Bensalem, Yves Blaquière, Yvon Savaria
In-FPGA Instrumentation Framework for OpenCL-Based Designs. IEEE Access 8 (2020)
Hachem Bensalem, Yves Blaquière, Yvon Savaria
Toward In-System Monitoring of OpenCL-Based Designs on FPGA. ISCAS (2019)
Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Safa Berrima, Yves Blaquière, Yvon Savaria
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integr. 62 (2018)
Mostafa Darvishi, Yves Audet, Yves Blaquière
Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA. CoRR (2018)
Etienne Lepercq, Yves Blaquière, Yvon Savaria
A pattern-based routing algorithm for a novel electronic system prototyping platform. Integr. 62 (2018)
Safa Berrima, Yves Blaquière, Yvon Savaria
Sub-ps resolution programmable delays implemented in a Xilinx FPGA. MWSCAS (2017)
Safa Berrima, Yves Blaquière, Yvon Savaria
A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. ISCAS (2017)
Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
Towards an efficient SEU effects emulation on SRAM-based FPGAs. Microelectron. Reliab. 66 (2016)
Wasim Hussain, Hussein Fakhoury, Patricia Desgreys, Yves Blaquière, Yvon Savaria
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2016)
Wasim Hussain, Yvon Savaria, Yves Blaquière
A compact spatially configurable differential input stage for a field programmable interconnection network. ISCAS (2016)
Wasim Hussain, Olivier Valorge, Yves Blaquière, Yvon Savaria
A novel spatially configurable differential interface for an electronic system prototyping platform. Integr. 55 (2016)
Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. IOLTS (2015)
Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. EWDTS (2015)
Wasim Hussain, Yves Blaquière, Yvon Savaria
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Gontran Sion, Yves Blaquière, Yvon Savaria
Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. IOLTS (2015)
Mostafa Darvishi, Yves Audet, Yves Blaquière, Claude Thibeault
Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. CoRR (2015)
Yves Blaquière, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria
Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. ISCAS (2014)
Nicolas Laflamme-Mayer, Yves Blaquière, Yvon Savaria, Mohamad Sawan
A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Nicolas Laflamme-Mayer, Mohamad Sawan, Yves Blaquière
A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. LASCAS (2013)
Mikael Guillemot, Yves Blaquière, Yvon Savaria
Software rendering methods to display wafer scale integrated circuit dataset. CCECE (2013)
Wasim Hussain, Yvon Savaria, Yves Blaquière
C protocol in the WaferBoard™. ISCAS (2013)
Karim Baratli, Ahmed Lakhssassi, Yves Blaquière, Yvon Savaria
A netlist pruning tool for an electronic system prototyping platform. NEWCAS (2013)
Nicolas Laflamme-Mayer, Walder Andre, Olivier Valorge, Yves Blaquière, Mohamad Sawan
Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Michel Sayde, Ahmed Lakhssassi, Mohammed Bougataya, Omar Terkawi, Yves Blaquière
SoC systems thermal monitoring using embedded sensor cells unit. MWSCAS (2012)
Omar Al-Terkawi Hasib, Walder Andre, Yves Blaquière, Yvon Savaria
Propagating analog signals through a fully digital network on an electronic system prototyping platform. ISCAS (2012)
Hai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquière
A new approach for pin detection for an electronic system prototyping reconfigurable platform. RSP (2012)
Mohamed Badreddine, Yves Blaquière, Mounir Boukadoum
Machine-learning framework for automatic netlist creation. ISCAS (2011)
Nicolas Laflamme-Mayer, Yves Blaquière, Mohamad Sawan
A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems. ICECS (2011)
Olivier Valorge, Yves Blaquière, Yvon Savaria
A spatially reconfigurable fast differential interface for a wafer scale configurable platform. ICECS (2010)
Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula
Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. ICECS (2010)
Etienne Lepercq, Yves Blaquière, Richard Norman, Yvon Savaria
Workflow for an Electronic Configurable Prototyping System. ISCAS (2009)
Olivier Valorge, Anh Tuan Nguyen, Yves Blaquière, Richard Norman, Yvon Savaria
Digital signal propagation on a wafer-scale smart active programmable interconnect. ICECS (2008)
Yan Basile-Bellavance, Etienne Lepercq, Yves Blaquière, Yvon Savaria
Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. ICECS (2008)
Yves Blaquière, Yvon Savaria, Jaouad El Fouladi
Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os. ICECS (2007)
Marc-André Cantin, Yves Blaquière, Yvon Savaria, Pierre Lavoie, Éric Granger
Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. ISCAS (2000)
Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. FCCM (1998)
Yves Blaquière, Michel Dagenais, Yvon Savaria
Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (2) (1996)
Yves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz
Cost analysis of a new algorithmic-based soft-error tolerant architecture. DFT (1995)
Yves Blaquière, Jacob Davidson
VHDL design of a priority interrupt controller and synchronizer for the MC68008. Microprocess. Microsystems 14 (7) (1990)