Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA.
Mostafa DarvishiYves AudetYves BlaquièrePublished in: CoRR (2018)
Keyphrases
- power reduction
- power dissipation
- high speed
- power consumption
- low power
- real time
- gate array
- destination node
- directed graph
- hardware implementation
- real time image processing
- digital signal processing
- shortest path
- hardware design
- data acquisition
- monitoring system
- cmos technology
- low cost
- graph structure
- path length
- single chip
- power saving
- signal processing
- network structure
- multicast tree
- logic circuits
- sensor networks